High k dielectric material and metal are adopted to form a gate stack when an integrated semiconductor device is scaled down to smaller device features through various technology nodes. In an integrated circuit with field-effect transistors (FETs), such as a metal-oxide-transistor (MOS), the threshold voltages for both p-type MOS (PMOS) transistors and n-type MOS (NMOS) transistors need to be adjusted, respectively for the device speed and performance characteristics. However, a doping process used to adjust the threshold voltages has limited effect when the feature size of the transistors is scaled down. What is needed is a device structure and a method of making the structure such that the work functions can be tuned independently and cost-effectively.